As pixel defects in a solid-state imaging device, there are a white defect in which a certain amount of electric charge is invariably added to a normal signal (derived from a crystalline defect or the like in a CCD (Charge Coupled Device)), and a black defect in which either a signal level decreases at a certain ratio (derived from scratches on on-chip lenses or the like of a CCD) or a signal level that is 0 or below is invariably output (derived from the opening of a photodiode of a CCD) with respect to a normal signal. These pixel defects become dot-like blemishes at the time of imaging and cause deterioration in image quality, so that various means for detecting and correcting defects by signal processing have been proposed.
With respect to pixel defect detecting and correcting apparatuses which have been conventionally disclosed, in general, pixel defects are detected at the time of adjustment, the positions thereof are stored in a memory device such as a register, those positions are referred to at the time of imaging, an interpolation value is calculated from data of pixels in the vicinity of the target pixel, and interpolation is executed by replacing the defect pixel data with this interpolation value.
For example, in paragraph No. [0018] in Patent Literature 1 is disclosed a mechanism in which correction of pixel defects and defect detection are executed concurrently with imaging; and in order for the number of defects which should be corrected regarding an imaging device to be within a predetermined setting range, a threshold value for level comparison concerning defect detection is variably set in response to the number of defect pixels, and also positional information on the defect pixels, the number of detected frames when the defect pixels have been detected as defect pixels also in frames prior to a present frame, and information showing whether or not correction has been performed in the frame immediately before regarding the defect pixels are stored in single memory means.
Further, in [structure] of ABSTRACT OF THE DISCLOSURE in Patent Literature 2 is disclosed an apparatus including a level difference detecting circuit which detects in a solid-state imaging device the level difference between a first pixel signal from the first pixel and a second pixel signal from a second pixel in the vicinity of the first pixel, a comparator which compares an output signal of this level difference detecting circuit with a predetermined threshold value, and a memory which stores comparison results of a plurality of fields obtained in this comparator; and defect pixels are determined using memory information of this memory.
Further, in [structure] of ABSTRACT OF THE DISCLOSURE in Patent Literature 3 is disclosed an apparatus including a system controller, a switch, and a pre-detection processing circuit which detect, based on an output signal of the CCD element, defect pixels outputting signals of specific levels from among pixels of a CCD element, and further a register which stores positional data on the defect pixels detected thereby; and in which the positional data stored in the resister are deleted.
Further, in [structure] of ABSTRACT OF THE DISCLOSURE in Patent Literature 4 is disclosed a mechanism in which when an inspection of defects is carried out, defect pixels are detected by comparing in a comparator the imaging output level of a CCD solid-state imaging device with a predetermined detection level; the number of these defect pixels detected is counted by a counter; when the detected number exceeds the number allowable in memory, defect-detecting sensitivity is lowered by setting in a detection level setting circuit the detection level of the comparator higher than before, and a re-inspection is repeated until the number of defect pixels becomes allowable.
[Patent Literature 1]
    Published Japanese Patent Application No. 2002-51266[Patent Literature 2]    Published Japanese Patent Application No. H6-284346[Patent Literature 3]    Published Japanese Patent Application No. H5-260385[Patent Literature 4]    Published Japanese Patent Application No. H6-315112